Method of producing semiconductor elements using a test structure

ABSTRACT

Testing the production of semiconductor elements on a substrate, the semiconductor elements having a plurality of cell types, by providing at least one test structure on the substrate with a number of test cells having cell types similar to one or more of the plurality of cell types, each of the cell types having at least a first and a second local interconnect layer structure to be connected to predetermined supply voltages during use, a plurality of first and second polysilicon layer structures to provide control voltages to first and second electronic component structures, respectively, connecting in the test structure all of the plurality of first polysilicon layer structures to one another to provide an interconnected first polysilicon layer structure, and connecting in the test structure all of the plurality of second polysilicon layer structures to one another to provide an interconnected second polysilicon layer structure, providing predetermined test voltages and measuring currents resulting from the test voltages to identify production errors.

The present invention relates to the testing of the production of atleast one semiconductor element in a semiconductor substrate.

U.S. Pat. No. 6,054,721 discloses a method of producing semiconductorelements on a semiconductor wafer using a predetermined test structurethat is produced on the same semiconductor wafer during the fabricationof the semiconductor elements. In order to detect undesired connectionsbetween conductive structures within the multiple layers on thesemiconductor wafer, the prior art discloses a method of producingfinger shaped layers in the test structure comprising conductive layershaving the same distances and orientations with respect to one anotheras in the semiconductor elements to be produced. The conductive layersin the test structure are designed such that they can be easilyconnected to a test arrangement for supplying voltages to the conductivelayer, in order to test undesired shorts between them. If the teststructure shows an undesired electrical short, most probably thesemiconductor elements on the same semiconductor wafer will also showsimilar undesired shorts.

In nowadays 0.18 micron technology (and smaller), the test structureprovided by this prior art document is not sufficient anymore. There isa need for an improved method of detecting defects during production ofCMOS 0.18 micron technology (and smaller).

Therefore, the invention provides a method of producing at least onesemiconductor element in a semiconductor substrate, the semiconductorelement having a plurality of cell types, the method comprising:

-   -   producing at least one test structure on the semiconductor        substrate,    -   comprising a predetermined number of test cells having cell        types similar to one or more of the plurality of cell types    -   each of the cell types having at least a first and second local        interconnect layer structure to be connected to predetermined        supply voltages during use, a plurality of first and second        polysilicon layer structures to provide control voltages to        first and second electronic component structures, respectively,    -   connecting in the test structure all of the plurality of first        polysilicon layer structures to one another to provide an        interconnected first polysilicon layer structure, and connecting        in the test structure all of the plurality of second polysilicon        layer structures to one another to provide an interconnected        second polysilicon layer structure;    -   providing predetermined test voltages to the first and second        local interconnect layer structures, and to the interconnected        first and second polysilicon layer structures, respectively;    -   measuring currents resulting from the test voltages to identify        production errors.

By interconnecting all of the first polysilicon layer structures to oneanother and interconnecting all the second polysilicon layer structuresin the test structure to one another there are basically four differentconductive structures in the test structure. By then providing differentvoltages of a predetermined value between those four conductivestructures, several kinds of potential electric shorts or leakagecurrents can be easily established. If the test structure shows suchundesired shorts or leakage currents, it may be assumed that thesemiconductor elements show these kinds of defects too.

Preferably, the test voltages are selected such that at least one of thefollowing production errors may be determined:

-   -   one or more electric shorts between the first and the second        polysilicon layer structures;    -   one or more electric shorts between at least one of the first        and second local interconnect layer structures and at least one        of the first and second polysilicon layer structures;    -   n-gate oxide leakages;    -   p-gate oxide leakages.

The present invention also relates to a semiconductor substratecomprising at least one semiconductor element, the semiconductor elementhaving a plurality of cell types, and at least one test structurecomprising a predetermined number of test cells having cell typessimilar to one or more of the plurality of cell types, each of the celltypes having at least a first and a second local interconnect layerstructure to be connected to predetermined supply voltages during use, aplurality of first and second polysilicon layer structures to providecontrol voltages to first and a second electronic component structures,respectively, in the test structure all of the plurality of firstpolysilicon layer structures being connected to one another to providean interconnected first polysilicon layer structure, and in the teststructure all of the plurality of second polysilicon layer structuresbeing connected to one another to provide an interconnected secondpolysilicon layer structure.

Finally, the present invention relates to a semiconductor devicecomprising such a substrate.

The present invention will be illustrated with reference to somedrawings which are only intended to explain the present invention butnot to limit its scope, which is limited only by the scope of theannexed claims.

FIG. 1 shows schematically a wafer and a plurality of reticles on thewafer during production of semiconductor elements;

FIG. 2 shows schematically one of the reticles of FIG. 1;

FIG. 3 shows schematically a block diagram of a test structure;

FIG. 4 shows schematically a top view of a portion of a YEM cell in thetest structure;

FIG. 5 a shows schematically a top view of a four-transistorconstruction in the semiconductor element to be tested;

FIG. 5 b shows schematically a top view of a four-transistor cell in theYEM structure used for testing the four-transistor structure of FIG. 5a;

FIGS. 6 a and 6 b show equivalent electric circuits of the structuresshown in FIGS. 5 a and 5 b, respectively;

FIG. 7 shows a schematic lateral section of two transistors of theequivalent circuit of FIG. 6 b.

FIG. 1 shows very schematically a circular wafer 1 made of asemiconductor material, e.g., silicon or any other applicablesemiconductor material known to persons skilled in the art. The waferis, e.g., 200 mm in diameter.

During the production of semiconductor elements on the wafer 1, aplurality of reticles 2 are produced on the wafer 1. There are, e.g., 50such reticles 2. The reticles 2, as is known to persons skilled in theart, may have the form of a square. Every reticle 2 comprises the samesemiconductor elements. Following the production of the semiconductorelements, the reticles 2 are separated from one another by sawing, as isknown to persons skilled in the art.

FIG. 2 shows an example of a reticle 2. The reticle 2 comprises aplurality of semiconductor elements 4. FIG. 2 shows two suchsemiconductor elements 4, however, there may be many more of suchsemiconductor elements 4. A saw line 7 shows where the reticle 2 will beseparated from its neighbours.

As is known to a person skilled in the art, the area 6 where the reticle2 is separated from its neighbours, may be provided with very smallproduct characterisation modules PCM. These PCMs comprise teststructures providing a limited possibility of characterising the processto produce the semiconductor elements 4.

The reticle 2 may also comprise one or more process evaluation modulesPEM 3. Such PEMs 3 are also known from the prior art and are used tomeasure process parameters as well as the data used for processdevelopment.

The reticle 2 also comprises at least one yield evaluation module YEM 5.Also YEMs are known from the prior art and are used for purposes ofyield verification. A limited number of these YEMs is available in viewof the limited reticle surface of, e.g., 4 cm².

The present invention relates to a modified YEM structure used fortesting.

FIG. 3 shows how the YEM 5 may be designed in accordance with theinvention. The YEM 5, e.g., comprises 16 different cell structures 5(1),. . . 5(16). Each of the cells 5(i), i=1, . . . 16, comprises aplurality of semiconductor elements with a similar structure as thesemiconductor elements 4 to be tested. FIG. 3 shows that these cells5(i) are arranged in 8 columns and 2 rows. However, there may beprovided other numbers of cells in other arrangements.

It has been found that, in most cases, a limited number of cells (e.g.16 as in the example of FIG. 3) may already be representative of a verylarge number of the electrical components in the semiconductor elements4. For instance, the table below shows that 16 cells with the highestnumber of electrical components in a DSP block (DSP=Digital SignalProcessing) in the semiconductor elements 4 may cover about 70% of thetotal area covered by the DSP block in the semiconductor element 4.Therefore, designing the YEM 5 with 16 cells with similar electroniccomponents as in the semiconductor element 4 results in a test structurerepresentative of the majority of electronic components in thesemiconductor elements 4.

Cell # function 1 nd2 3508 input NAND 2 rdmr_fd1sqx2 2290 flip flop 3 Iv2057 inverter 4 Ao2 1777 input BOOLEAN 5 Ao3a 1207 input BOOLEAN 6gate_decap9 1158 decoupling cell 7 mux21 1021 input MUX 8 Nd3 927 inputNAND 9 Nr2 905 input NOR 10 Nd2a 575 input NAND 11 Ao7a 551 inputBOOLEAN 12 En2 479 input OBSOLETE 13 Ao2n 448 input BOOLEAN 14 Bf1tx2428 plain BUFFER 15 a06 344 input BOOLEAN 16 Eo2 332 input OBSOLETE Eo2total added area 0.462 mm2 total area dsp 0.666 mm2 covered 69.4%

FIG. 4 shows a top view of an exemplary YEM cell portion in accordancewith the invention. The YEM structure comprises a plurality ofelectrical components that are interconnected in a predetermined way inorder to be able to perform the desired electrical tests.

FIG. 4 shows four metal lines/connections 16(1), 16(2), 16(3), 16(4) ofthe same metal layer on top of the cell structure. Below the metal lines16(1) . . . 16(4), there are provided several local interconnectionlayer (LIL) structures 10. Usually these local interconnection layersare made of polysilicon, polysilicon having a silicide layer on top ofit, or metal, as is known to a person skilled in the art.

In a layer below the metal lines 16(1), . . . 16(4), there are providedpolysilicon layers 12, usually, to connect gates of transistors tocontrol voltages to control the operation of the transistors. In thepresent structure, there are at least 2 sets of different polysilicionlayers where portions of one set are not allowed to show electricalshorts to portions of the other set.

The test structure also comprises source and drain regions 18.

Electrical contacts between the metal lines 16(1), . . . 16(4) andunderlying polysilicon layers 12 and LIL 10 are indicated with referencenumbers 14.

The structure of the YEM cell is similar to, but not equal to, theassociated cell structures used in the semiconductor elements 4. Thiswill be further explained with reference to FIGS. 5 a and 5 b. Inaccordance with the invention, in the YEM structure, the polysiliconstructure 12, the LIL structure 10, as well as the source and drain 18are equal to the respective same areas in the original electricalcomponents in the semiconductor elements 4. Only the metal lines 16(1),. . . 16(4) and their connections to the underlying structures have beenamended to provide for an easy test environment.

FIG. 5 a shows an original four-transistor cell of a semiconductorelement 4. FIG. 5 b shows a portion of FIG. 4 on an enlarged scale andreflects how the original structure of FIG. 5 a is modified in the YEMcell. The same reference numbers as in FIG. 4 refer to the same areas.So, FIG. 5 a shows a structure of which potential production errors willbe identified not by testing the structure of FIG. 5 a itself but bytesting the structure of 5 b that has been changed relative to FIG. 5 aas is further explained below. FIG. 5 a shows that the originalstructure comprises other metal lines, here referenced 15(1), . . .15(5), than the modified structure of FIG. 5 b. E.g., in FIG. 5 a, metalline 15(5) is connected to a LIL 10(2) (and normally also to ground),whereas in FIG. 5 b, the corresponding metal line 16(4) is additionallyconnected to a drain of one of the transistors. Also the other metallines 15(1), . . . 15(4) have other areas and connections thancorresponding metal lines 16(1), . . . 16(3) in FIG. 5 b. E.g., metalline 15(1) in FIG. 5 a is connected both to a LIL 10(1) and asource/drain area 18 whereas in FIG. 5 b, metal line 16(1) is onlyconnected to the LIL 10(1).

The metal line 16(1) is to be connected to a first power supply voltage,whereas the metal line 16(4) is to be connected to a second power supplyvoltage.

FIGS. 5 a and 5 b show that in the four-transistor cell arrangementthere are two different polysilicon lines 12(1), 12(2). Regions 18(1)and 18(2) define source and drain regions for the four transistors.

Metal line 16(2) is used to interconnect all polysilicon layerstructures 12(2) in the entire cell, and the metal line 16(3) is used tointerconnect all polysilicon layer structures 12(1) in the entire cell.

FIG. 6 a shows an equivalent electronic circuit of the structure shownin FIG. 5 a. It comprises four transistors T1, T2, T3, T4. All thetransistors are MOS transistors. Transistors T1 and T2 are PMOStransistors, whereas transistors T3 and T4 are NMOST transistors. Thetransistors T1, T2 have sources connected to a power supply line Vdd,e.g., 1.8V. The drains of the transistors T1, T2 are connected to oneanother and provide an output Outp Z.

The drains of the transistors T1, T2 are also connected to a source oftransistor T3. Transistor T3 has its drain D connected to source S oftransistor T4. Transistor T4 has its drain D connected to power supplyvoltage Vss, e.g., being on ground level 0V.

Transistors T1, T3 have gates connected to a common input line Inp A.Transistors T2, T4 have gates connected to an input line Inp B.

FIG. 6 b shows an equivalence circuit of the structure shown in FIG. 5b. It also shows a four transistor cell, however, arranged in a slightlydifferent way than the structure of FIG. 6 a. FIG. 6 b shows that thefour-transistor cell is arranged as two CMOS structures. Transistors T5,T6 are arranged as a first CMOS structure having their gates jointlyconnected to the polysilicon line 12(1), also indicated in FIG. 6 b with“pol1”.

Transistors T7, T8 are arranged as a second CMOS structure having theirgates connected to a second polysilicon line 12(2), in FIG. 6 b alsoindicated with “pol2”.

Moreover FIG. 6 b shows how the areas 16(1), 16(4), 18(1), 18(2)correspond to electrical connections of the equivalent electroniccircuit.

Although the equivalent electronic circuit of FIG. 6 b differs from theelectronic circuit of the electronic components in the semiconductorelements 4, as shown in FIG. 6 a, the basic structures of LIL 10,polysilicon 12, and source and drain regions 18 do have the samerelative locations in the YEM structure. Only the way they areinterconnected in the YEM structure by the metal lines 16(1), . . .16(4) differs such that an easy test measurement can be performed.

The arrangement of FIG. 5 b allows for instance to make the followingtest measurements in the YEM structure, as indicated in the table below.

pol1 pol2 lil1 lil2 [V] [V] [V] [V] polpol shorts 0 1.8 1.8 0 polLILshorts 0 0 1.8 1.8 Nmost leakage 1.8 1.8 1.8 0 Pmost leakage 0 0 1.8 0Where:

polpo1 shorts=electrical shorts between pol1 and pol2 structures in theYEM structure;

polLIL shorts=electrical shorts between one or more of the pol1 and pol2structures and one or more of the LIL and LIL1 and LIL2 structures (cf.FIG. 6 b);

Nmost leakage=leakage currents through the Nmost T6, T8 (cf. FIG. 6 b);

Pmost leakage=leakage currents in Pmost T5, T7 (cf. FIG. 6 b).

After applying the voltages as indicated in the table above, no currentsmay be detected when the structures are located correctly. If currents(above a predetermined threshold level) are detected, one or more of theerrors indicated above are present. If these errors are present in theYEM structure, one can conclude that, most probably, similar defects arepresent in the semiconductor elements 4 in the same reticle 2.

FIG. 7, finally, shows a schematic lateral view of transistors T5 and T6of the circuit shown in FIGS. 5 b and 6 b. The transistor T5 isconnected with its source 26 to lil1 line 10 via a contact 36.Transistor T5 comprises a gate 27 separated from an Nwell 22 by means ofan insulating layer (not shown). Transistor T5 comprises a drain 28.

Transistor T5 also comprises an N+ region 24 connected to lil1 line 10via a contact 38 for providing the Nwell 22 with an appropriate biasvoltage.

Transistor T6 is arranged directly in a P substrate 20 and is providedwith a drain 30, a source 32 and a gate 31. The source 32 is connectedto lil2 line 10 via a contact 40. Transistor T6 comprises a P+ region 34connected to lil2 line 10 via a contact 42 for providing the substratewith a proper bias voltage.

The gates 27, 31 of the transistors T5, T6 are interconnected bypolysilicon line 12(1) (pol1).

Although the present invention has been illustrated with reference to afour-transistor structure (FIGS. 5 a and FIGS. 5 b), and especially witha CMOS structure as a test structure (FIGS. 5 b and 6 b), the presentinvention is not limited to these types of electrical components in thecell structures. Other cell types and electrical components in thesemiconductor elements 4 and in the YEM structure may be provided.

Moreover, the present invention is in no way limited to the doping typesgiven in, e.g., FIG. 7. Other dopings may be provided, if necessary.

1. Method of producing at least one semiconductor element in asemiconductor substrate, the semiconductor element having a plurality ofcell types, the method comprising: producing at least one test structureon said semiconductor substrate, comprising a predetermined number oftest cells having cell types similar to one or more of said plurality ofcell types; each of said cell types having at least a first and a secondlocal interconnect layer structure to be connected to predeterminedsupply voltages during use, a plurality of first and second polysiliconlayer structures to provide control voltages to first and secondelectronic component structures, respectively; connecting in said teststructure all of said plurality of said first polysilicon layerstructures to one another to provide an interconnected first polysiliconlayer structure, and connecting in said test structure all of saidplurality of said second polysilicon layer structures to one another toprovide an interconnected second polysilicon layer structure; providingpredetermined test voltages to said first and second local interconnectlayer structures, and to said interconnected first and secondpolysilicon layer structures, respectively; measuring currents resultingfrom said test voltages to identify production errors.
 2. Methodaccording to claim 1, wherein said plurality of said first and secondpolysilicon layer structures are connected to one another using metalconnection structures.
 3. Method according to claim 1, wherein said teststructure comprises CMOS transistors.
 4. Method according to claim 1,wherein said test voltages are selected such that at least one of thefollowing production errors may be determined: one or more electricalshorts between said first and second polysilicon layer structures; oneor more electrical shorts between at least one of said first and secondlocal interconnect layer structures and at least one of said first andsecond polysilicon layer structures; n-gate oxide leakages; p-gate oxideleakages.
 5. Method according to claim 1, wherein said at least onesemiconductor element is located in one of a plurality of reticles on asemiconductor wafer.
 6. A semiconductor substrate comprising at leastone semiconductor element, the semiconductor element having a pluralityof cell types, and at least one test structure comprising apredetermined number of test cells having cell types similar to one ormore of said plurality of cell types, each of said cell types having atleast a first and a second local interconnect layer structure to beconnected to predetermined supply voltages during use, a plurality offirst and second polysilicon layer structures to provide controlvoltages to first and second electronic component structures,respectively, in said test structure all of said plurality of said firstpolysilicon layer structures being connected to one another to providean interconnected first polysilicon layer structure, and in said teststructure all of said plurality of said second polysilicon layerstructures being connected to one another to provide an interconnectedsecond polysilicon layer structure.
 7. A semiconductor device comprisinga substrate according to claim 6.